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<p>MIPI CSI Rx Subsystem configuration structure.  
 <a href="struct_x_csi_ss___config.html#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a33f6c7eabb77aeaf4b942d50de261bb2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a33f6c7eabb77aeaf4b942d50de261bb2">DeviceId</a></td></tr>
<tr class="memdesc:a33f6c7eabb77aeaf4b942d50de261bb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#a33f6c7eabb77aeaf4b942d50de261bb2">More...</a><br/></td></tr>
<tr class="separator:a33f6c7eabb77aeaf4b942d50de261bb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:accf7178f1f7fc0ba40fee2e61ca159bc"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#accf7178f1f7fc0ba40fee2e61ca159bc">BaseAddr</a></td></tr>
<tr class="memdesc:accf7178f1f7fc0ba40fee2e61ca159bc"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> BaseAddress is the physical base address
</pre><p> of the subsystem address range  <a href="#accf7178f1f7fc0ba40fee2e61ca159bc">More...</a><br/></td></tr>
<tr class="separator:accf7178f1f7fc0ba40fee2e61ca159bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a47c248f223217fb36480fd87299817b0"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a47c248f223217fb36480fd87299817b0">HighAddr</a></td></tr>
<tr class="memdesc:a47c248f223217fb36480fd87299817b0"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> HighAddress is the physical MAX address
</pre><p> of the subsystem address range  <a href="#a47c248f223217fb36480fd87299817b0">More...</a><br/></td></tr>
<tr class="separator:a47c248f223217fb36480fd87299817b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af827137dd9214be2086a9cb6c866b6fc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#af827137dd9214be2086a9cb6c866b6fc">IsIicPresent</a></td></tr>
<tr class="memdesc:af827137dd9214be2086a9cb6c866b6fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for IIC presence in subsystem.  <a href="#af827137dd9214be2086a9cb6c866b6fc">More...</a><br/></td></tr>
<tr class="separator:af827137dd9214be2086a9cb6c866b6fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a161805ed2b55c724c987115b5c0b376a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a161805ed2b55c724c987115b5c0b376a">LanesPresent</a></td></tr>
<tr class="memdesc:a161805ed2b55c724c987115b5c0b376a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of PPI Lanes in the design.  <a href="#a161805ed2b55c724c987115b5c0b376a">More...</a><br/></td></tr>
<tr class="separator:a161805ed2b55c724c987115b5c0b376a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a203422f11e21168679180a7060553199"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a203422f11e21168679180a7060553199">PixelCount</a></td></tr>
<tr class="memdesc:a203422f11e21168679180a7060553199"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Pixels per clock 1,2,4.  <a href="#a203422f11e21168679180a7060553199">More...</a><br/></td></tr>
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<tr class="memitem:a7c808fba33fd373f15f4c7e98bea29b9"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a7c808fba33fd373f15f4c7e98bea29b9">PixelFormat</a></td></tr>
<tr class="memdesc:a7c808fba33fd373f15f4c7e98bea29b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">The pixel format selected from all RGB, RAW and YUV422 8bit options.  <a href="#a7c808fba33fd373f15f4c7e98bea29b9">More...</a><br/></td></tr>
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<tr class="memitem:a96e356d9a84ea1e476fcca77b4061dcc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a96e356d9a84ea1e476fcca77b4061dcc">VcNo</a></td></tr>
<tr class="memdesc:a96e356d9a84ea1e476fcca77b4061dcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Virtual Channels supported by system.  <a href="#a96e356d9a84ea1e476fcca77b4061dcc">More...</a><br/></td></tr>
<tr class="separator:a96e356d9a84ea1e476fcca77b4061dcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b108e8ca479ecd320c08d66cb808e72"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a2b108e8ca479ecd320c08d66cb808e72">CsiBuffDepth</a></td></tr>
<tr class="memdesc:a2b108e8ca479ecd320c08d66cb808e72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line buffer Depth set.  <a href="#a2b108e8ca479ecd320c08d66cb808e72">More...</a><br/></td></tr>
<tr class="separator:a2b108e8ca479ecd320c08d66cb808e72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0858f6d6032b5f521f2630737c3ecbb"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#af0858f6d6032b5f521f2630737c3ecbb">IsEmbNonImgPresent</a></td></tr>
<tr class="memdesc:af0858f6d6032b5f521f2630737c3ecbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for presence of Embedded Non Image data.  <a href="#af0858f6d6032b5f521f2630737c3ecbb">More...</a><br/></td></tr>
<tr class="separator:af0858f6d6032b5f521f2630737c3ecbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af96d74b947652a7cdd48c66eac494ecd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#af96d74b947652a7cdd48c66eac494ecd">IsDphyRegIntfcPresent</a></td></tr>
<tr class="memdesc:af96d74b947652a7cdd48c66eac494ecd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag for DPHY register interface presence.  <a href="#af96d74b947652a7cdd48c66eac494ecd">More...</a><br/></td></tr>
<tr class="separator:af96d74b947652a7cdd48c66eac494ecd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9f231140e4e8a641b6a0bcfbf3a245fc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a9f231140e4e8a641b6a0bcfbf3a245fc">DphyLineRate</a></td></tr>
<tr class="memdesc:a9f231140e4e8a641b6a0bcfbf3a245fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY Line Rate ranging from 80-1500 Mbps.  <a href="#a9f231140e4e8a641b6a0bcfbf3a245fc">More...</a><br/></td></tr>
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<tr class="memitem:a87c8dcd4a84e413201c4718c97094aa0"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a87c8dcd4a84e413201c4718c97094aa0">EnableCrc</a></td></tr>
<tr class="memdesc:a87c8dcd4a84e413201c4718c97094aa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">CRC Calculation optimization enabled.  <a href="#a87c8dcd4a84e413201c4718c97094aa0">More...</a><br/></td></tr>
<tr class="separator:a87c8dcd4a84e413201c4718c97094aa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f1b9fcb8ab6b865cbfe8a113ddfa273"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a8f1b9fcb8ab6b865cbfe8a113ddfa273">EnableActiveLanes</a></td></tr>
<tr class="memdesc:a8f1b9fcb8ab6b865cbfe8a113ddfa273"><td class="mdescLeft">&#160;</td><td class="mdescRight">Active Lanes programming optimization enabled.  <a href="#a8f1b9fcb8ab6b865cbfe8a113ddfa273">More...</a><br/></td></tr>
<tr class="separator:a8f1b9fcb8ab6b865cbfe8a113ddfa273"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1eef0b961af42e305aecfaeaf6e203f6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#a1eef0b961af42e305aecfaeaf6e203f6">IicInfo</a></td></tr>
<tr class="memdesc:a1eef0b961af42e305aecfaeaf6e203f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC sub-core configuration.  <a href="#a1eef0b961af42e305aecfaeaf6e203f6">More...</a><br/></td></tr>
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<tr class="memitem:ab0e69785dbdf558a6a79296eb2485e7a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#ab0e69785dbdf558a6a79296eb2485e7a">CsiInfo</a></td></tr>
<tr class="memdesc:ab0e69785dbdf558a6a79296eb2485e7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">CSI sub-core configuration.  <a href="#ab0e69785dbdf558a6a79296eb2485e7a">More...</a><br/></td></tr>
<tr class="separator:ab0e69785dbdf558a6a79296eb2485e7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1d8bc1de669bafd1619a221002416db"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi_ss___config.html#ad1d8bc1de669bafd1619a221002416db">DphyInfo</a></td></tr>
<tr class="memdesc:ad1d8bc1de669bafd1619a221002416db"><td class="mdescLeft">&#160;</td><td class="mdescRight">DPHY sub-core configuration.  <a href="#ad1d8bc1de669bafd1619a221002416db">More...</a><br/></td></tr>
<tr class="separator:ad1d8bc1de669bafd1619a221002416db"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>MIPI CSI Rx Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="accf7178f1f7fc0ba40fee2e61ca159bc"></a>
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          <td class="memname">UINTPTR XCsiSs_Config::BaseAddr</td>
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<p><pre class="fragment"> BaseAddress is the physical base address
</pre><p> of the subsystem address range </p>

<p>Referenced by <a class="el" href="xcsiss__intr__example_8c.html#a6fb058d3bf941cd9a817bb6ad7e0a819">CsiSs_IntrExample()</a>, <a class="el" href="xcsiss__selftest__example_8c.html#a670a4c28d6e2f3b6341f0f261a7a1835">CsiSs_SelfTestExample()</a>, <a class="el" href="pipeline__program_8h.html#a9af254929ec07e0b8e29ff28e18ec709">InitializeCsiRxSs()</a>, and <a class="el" href="group__csiss.html#ga8fde229b1ad93697e0cf3f1710b2db7e">XCsiSs_CfgInitialize()</a>.</p>

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          <td class="memname">u32 XCsiSs_Config::CsiBuffDepth</td>
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<p>Line buffer Depth set. </p>

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          <td class="memname"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a> XCsiSs_Config::CsiInfo</td>
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<p>CSI sub-core configuration. </p>

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<a class="anchor" id="a33f6c7eabb77aeaf4b942d50de261bb2"></a>
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          <td class="memname">u32 XCsiSs_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

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          <td class="memname"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a> XCsiSs_Config::DphyInfo</td>
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<p>DPHY sub-core configuration. </p>

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<p>DPHY Line Rate ranging from 80-1500 Mbps. </p>

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<p>Active Lanes programming optimization enabled. </p>

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<p>CRC Calculation optimization enabled. </p>

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<p><pre class="fragment"> HighAddress is the physical MAX address
</pre><p> of the subsystem address range </p>

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          <td class="memname"><a class="el" href="struct_csi_rx_ss_sub_core.html">CsiRxSsSubCore</a> XCsiSs_Config::IicInfo</td>
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<p>IIC sub-core configuration. </p>

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<p>Flag for DPHY register interface presence. </p>

<p>Referenced by <a class="el" href="group__csiss.html#gaf30fdaf13ba08d8612f8e20ab21d8ff2">XCsiSs_Activate()</a>, <a class="el" href="group__csiss.html#ga8fde229b1ad93697e0cf3f1710b2db7e">XCsiSs_CfgInitialize()</a>, and <a class="el" href="group__csiss.html#ga3c63d232d9c7c19a7206fe10d5713509">XCsiSs_ReportCoreInfo()</a>.</p>

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<p>Flag for presence of Embedded Non Image data. </p>

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<p>Flag for IIC presence in subsystem. </p>

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          <td class="memname">u32 XCsiSs_Config::LanesPresent</td>
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<p>Number of PPI Lanes in the design. </p>

<p>Referenced by <a class="el" href="group__csiss.html#ga32e53cbe89a9acc42816e016c39e1cd6">XCsiSs_GetLaneInfo()</a>.</p>

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<p>Number of Pixels per clock 1,2,4. </p>

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<p>The pixel format selected from all RGB, RAW and YUV422 8bit options. </p>

<p>Referenced by <a class="el" href="pipeline__program_8h.html#a27a98e798ed33a22a64a35485322bbdc">SetColorDepth()</a>.</p>

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<p>Number of Virtual Channels supported by system. </p>
<p>This can range from 1 - 4 to ALL </p>

<p>Referenced by <a class="el" href="group__csiss.html#gae291a001aba0f4141b360de5195ee81e">XCsiSs_GetVCSelection()</a>, and <a class="el" href="group__csiss.html#ga038b595c1a424408b3ee277a8496e8cf">XCsiSs_SetVCSelection()</a>.</p>

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